| Call Number | 11293 |
|---|---|
| Day & Time Location |
W 6:10pm-8:00pm 451 Computer Science Building |
| Points | 3 |
| Grading Mode | Standard |
| Approvals Required | None |
| Instructors | Franjo Ivancic - e-mail, homepage Michael Theobald - e-mail, homepage |
| Type | LECTURE |
| Method of Instruction | In-Person |
| Course Description | Introduction to the theory and practice of formal methods for the design and analysis of correct (i.e. bug-free) concurrent and embedded hardware/software systems. Topics include temporal logics; model checking; deadlock and liveness issues; fairness; satisfiability (SAT) checkers; binary decision diagrams (BDDs); abstraction techniques; introduction to commercial formal verification tools. Industrial state-of-art, case studies and experiences: software analysis (C/C++/Java), hardware verification (RTL). |
| Web Site | Vergil |
| Department | Computer Science |
| Enrollment | 68 students (70 max) as of 9:07PM Friday, July 26, 2024 |
| Subject | Computer Science and Electrical Engineering |
| Number | E6863 |
| Section | 001 |
| Division | School of Engineering and Applied Science: Graduate |
| Open To | Barnard College, Columbia College, Engineering:Undergraduate, Engineering:Graduate, GSAS, General Studies, Journalism |
| Section key | 20233CSEE6863E001 |